In recent years, with advancement of digital technologies of electronic hardware, semiconductor memory devices which have large capacities and are nonvolatile have been vigorously developed to store data of music, image, information, etc. For example, a nonvolatile memory device incorporating ferroelectric as a capacitive element is used in many fields. In contrast to the nonvolatile memory device incorporating the ferroelectric capacitor, a nonvolatile memory device incorporating magnetoresistive effect memory element, for example, a TMR element, a nonvolatile memory device (hereinafter referred to as ReRAM) incorporating a resistance variable memory element (resistance variable element) which switches resistance values in response to electric pulses applied thereto and retains the switched states, and so on have attracted an attention, because they have a high compatibility with a standard semiconductor process and enable miniaturization.
An exemplary structure for achieving high-dense integration in the nonvolatile memory device is a cross point structure (see Patent document 1). In this nonvolatile memory device having the cross point structure, plural memory elements respectively including resistance variable elements are arranged in array and these resistance variable elements are provided inside via holes at cross sections of plural first wires and plural second wires extending in parallel with each other in a direction crossing the first wires. To selectively activate a specified memory element selected from among the plural memory elements arranged in array, elements (non-linear elements or current control elements) having non-linear current and voltage characteristics are respectively placed in series with the resistance variable elements. The Patent document 1 discloses that bidirectional current control is achieved by using MIM diodes as the non-linear elements.
There is also known a configuration in which a memory element (resistance variable element) and a control element (current control element) are arranged adjacent each other horizontally instead of vertically as disclosed in the Patent document 1 and the cross-sectional area of the memory element is made smaller than the cross-sectional area of the control element, thereby enabling the memory element to switch its state at a lower energy level than the control element (e.g., Patent document 2). Patent document 2 intends to provide an economical and large-capacity memory structure using such a configuration.    Patent document 1: U.S. Pat. No. 6,753,561 Specification    Patent document 2: Japanese Laid-Open Patent Application Publication No. 2004-6777